The present invention relates generally logic circuits, and more particularly to logic circuits used for address decoding.
Semiconductor devices, such as semiconductor memories, use address decoders to selectively activate a memory cell based on an external address or an internally generated address. During read, write, refresh (DRAM) and erase (EPROM) cycles, decoders can be activated. These decoders will typically be directly in the critical speed path of the device.
An example of a conventional logic circuit, that may be used as a decoder, is set forth in FIG. 13 and is designated by the general reference character 1300. Conventional logic circuit 1300 contains an input circuit 1310 and a driver circuit 1320. Input circuit 1310 is a conventional Complementary Metal Oxide Semiconductor (CMOS) 3-input NAND gate containing three n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) (N12-N14) connected in series between ground (GND) and a logic evaluation node V13. The input circuit also contains three p-channel MOSFETS (P6-P8) connected in parallel between a high power supply (VCC) and logic evaluation node V13. The MOSFETS (N12-N14 and P6-P8) are configured so that each n-channel MOSFET (N12-N14) and each p-channel MOSFET (P6-P8) receives a single input (A13-C13). If all the inputs (A13-C13) are at a logic high level, then conventional logic circuit 1300 is in a selected state and logic evaluation node V13 is pulled to GND, which corresponds to a low logic level, through n-channel MOSFETs (N12-N14). If any of the inputs (A13-C13) are at a logic low level then at least one of the n-channel MOSFETs (N12-N14) will be turned off and at least one of the p-channel MOSFETs (P6-P8) will be turned on. Thus, logic evaluation node V13 will be pulled to a high logic level VCC, which corresponds to an unselected state.
It is noted that each input is received at the gate of one n-channel MOSFET (N12-N14) and one p-channel MOSFET (P6-P8). This causes an input (A13-C13) to be loaded by a relatively large gate capacitance. Considering that inputs (A13-C13) are typically addresses and are connected to a large number of such logic circuits 1300, waveforms of the inputs (A13-C13) can rise and fall slowly, and/or be rounded at the corners. This can cause reduced circuit operation speeds and also can cause extended time periods of flow through current in which current flows through the input circuit 1310 directly from VCC to GND.
Driver circuit 1320 is connected to receive the logic level at logic evaluation node V13 and produces a logic output D13. Driver circuit 1320 is two inverters (INV11 and INV12) connected in series. The inverters (INV11 and INV12) are CMOS inverters, thus each contain an n-channel MOSFET and p-channel MOSFET. Inverter INV12 uses relatively large MOSFETs in order to drive a highly capacitive signal line connected to logic output D13. Because inverter INV12 is a CMOS inverter, the logic output D13 is driven from rail to rail (VDD to GND and vice-versa). This can cause unwanted power consumption due to the charging and discharging of the highly capacitive signal line connected to logic output D13.
A p-channel MOSFET will typically source less current than an n-channel MOSFET of the same size due to the lower mobility of the majority carriers or xe2x80x9choles.xe2x80x9d Thus, it may take a longer time for logic output D13 to achieve a trip-point or threshold of the receiving circuit (not shown) when going from logic low to logic high.
Also, the use of a p-channel MOSFET and an n-channel MOSFET in the inverter INV12 can cause circuit layout inefficiencies because there is a minimum device isolation distance required from an MOSFET and the edge of the well or tank. Because an n-channel and a p-channel MOSFET device is being used, both p-well and n-well regions can be required, this can require two such minimum device isolation distances, thus creating a larger layout area.
Another example of a conventional logic circuit, that may be used as a decoder, is set forth in FIG. 14 and is designated by the general reference character 1400. Conventional logic circuit 1400 contains an input circuit 1410, a driver circuit 1420 and a load circuit 1430. The input circuit 1410 has three n-channel MOSFETs (N15-N17) that are configured in the same manner as the three n-channel MOSFETs (N12-N14) in the input circuit 1310 of FIG. 13. Driver circuit 1420 of FIG. 14 is configured in the same manner as driver circuit 1320 of FIG. 13. Conventional logic circuit 1400 of FIG. 14 also has a load circuit 1430. The load circuit 1430 has a p-channel MOSFET P9 having a source connected to VCC, a drain connected to logic evaluation node V14 and a gate connected to GND.
In a selected state, conventional logic circuit 1400 receives inputs A14-C14 which all are logic high. Thus, all three series connected n-channel MOSFETs (N15-N17) are turned on. The n-channel MOSFETs (N15-N17) are sized to have a series resistance that is significantly less than the resistance of p-channel MOSFET P9 when the n-channel MOSFETs (N15-N17) are turned on. Therefore, when all inputs (A14-C14) are at a logic high, logic evaluation node V14 is pulled low enough to be seen as a logic low, which is then output by driver circuit 1420 at logic output D14.
When any of the inputs (A14-C14) have a logic low level, at least one of the n-channel MOSFETs (N15-N17) is turned off, thus logic evaluation node V14 is pulled high through p-channel MOSFET P9.
Conventional logic circuit 1400 of FIG. 14 has a smaller input capacitance than the logic circuit 1300 of FIG. 13. However, due to the need keep the ratio between the impedance of p-channel MOSFET P9 and the impedance of series n-channel MOSFETs (N15-N17) low, p-channel MOSFET P9 will typically be a relatively weak device. Thus, the pull-up speed of logic evaluation node V14 is slow, which can adversely delay the rising edge of logic output D14. Conversely, if the p-channel MOSFET P9 is made stronger, then the pull-down speed of logic evaluation node V14 can become slow.
Conventional logic circuit 1400 of FIG. 14 can also have the same current consumption and trip-point problems due to the rail-to-rail output of inverter INV14 as conventional logic circuit 1300 of FIG. 13.
Another example of a conventional logic circuit, that may be used as a decoder, is set forth in FIG. 15 and is designated by the general reference character 1500. The conventional logic circuit 1500 contains an input circuit 1510, a driver circuit 1520 and a load circuit 1530. In conventional logic circuit 1500, driver circuit 1520 and load circuit 1530 are constructed and operate generally in the same manner as driver circuit 1420 and load circuit 1430 in conventional logic circuit 1400 of FIG. 14.
Input circuit 1510 contains two n-channel MOSFETs (N18 and N19) connected in series between logic determination node V15 and input C15. N-channel MOSFETs (N18 and N19) receive inputs A15 and B15, respectively, at their gates.
In a selected state, conventional logic circuit 1500 receives inputs A15 and B15, which are logic high, and input C15 which is at a logic low. Thus, both series connected n-channel MOSFETs (N18 and N19) are turned on and pass the logic low level of input C15 to logic evaluation node V15. N-channel MOSFETs (N18 and N19) are sized to have a series resistance that is significantly less than the resistance of p-channel MOSFET P10 when n-channel MOSFETs (N18 and N19) are turned on. Therefore, when in a selected state, logic evaluation node V15 is pulled low enough to be seen as a logic low which is then output by driver circuit 1520 at logic output D15.
In a worst case select to deselect transition, one of inputs (A15 or B15) changes to logic low level, at least one of the n-channel MOSFETs (N18 and N19) is turned off, thus logic evaluation node V15 is pulled high through p-channel MOSFET P10.
The logic circuit 1500 of FIG. 15 has a smaller input capacitance than the logic input circuit 1300 of FIG. 13. However, due to the need keep the ratio between the impedance of p-channel MOSFET P10 and the impedance of series n-channel MOSFETs (N18 and N19) low, p-channel MOSFET P10 will typically be a relatively weak device. Thus, the pull-up speed of logic evaluation node V15 can be slow, which can adversely delay the rising edge of logic output D15. Conversely, if the p-channel MOSFET P10 is made stronger, then the pull-down speed of logic evaluation node V15 can become slow.
The conventional logic circuit 1500 of FIG. 15 can also have the same current consumption and trip-point problems due to the rail-to-rail output of inverter INV16 as the conventional logic circuit 1300 of FIG. 13.
In view of the above discussion, it would be desirable to provide a logic circuit that can have an improved propagation delay over conventional approaches. It would also be desirable to reduce current consumption in driving capacitive output signal lines.
According to the present embodiments, logic circuit includes an input circuit, an output circuit and a load circuit. The input circuit can receive logic inputs and generate a logic evaluation signal at a logic evaluation node. The output circuit can receive the logic evaluation signal and produce a logic output having a voltage swing that is less than a rail-to-rail swing. The output circuit can generate a feedback signal that can control the impedance of the load circuit. The load circuit can be coupled to the logic evaluation node and act as an active load of variable impedance.
According to one aspect of the embodiments, the logic input can include IGFETs of the same conductivity type connected in series and having gates that can receive logic input signals. Another logic input signal can be provided as a source input to one of the IGFETs.
According to another aspect of the embodiments, the output circuit can include two IGFETs of the same conductivity type acting as pull-up and pull-down drivers for the logic output. The logic output can have a voltage swing less than the rail-to-rail voltage of the high and low power supply voltages.
According to another aspect of the embodiments, the output circuit can include inverters coupled to receive the voltage at the logic evaluation node and produce control signals for the gates of the pull-up and pull-down drivers.
According to another aspect of the embodiments, the output circuit produces a feedback signal to control the impedance of the load circuit. The feedback signal can be the logic output.
According to another aspect of the embodiments, the feedback signal controlling the impedance of the load circuit can be generated from an inverter or inverters that are coupled to receive the logic evaluation node as an input.
According to another aspect of the embodiments, the output circuit can produce a logic output that is of the same polarity as the logic evaluation node.
According to another aspect of the embodiments, the output circuit can produce a logic output that is a logical inversion of the logic evaluation node.
According to another aspect of the embodiments, the load circuit can include an IGFET having a controllable impedance path coupled between a power supply and the logic evaluation node.
According to another aspect of the embodiments, the impedance path of the load circuit can be controlled by a feedback signal having a voltage swing less than a rail-to-rail voltage of the high and low power supplies.
According to another aspect of the embodiments, the load circuit can include a transistor acting as a voltage limiter to the feedback signal controlling the impedance path of an IGFET acting as an active load.
According to another aspect of the embodiments, the load circuit can include an inverter, acting as a voltage limiter to the feedback signal controlling the impedance path of an IGFET acting as an active load.
According to another aspect of the embodiments, logic circuits can be used in a multi-stage decoding scheme in which decoded signals can have a reduced voltage swing.
According to another aspect of the embodiments, logic circuits can have a critical path coupled to a source drive input, such that the critical path can have a reduced capacitive load.